In order to drive vertical lines of display panels such as liquid crystal panels, display drivers are used. In the display drivers, display driver circuits are mounted in a number corresponding to the number of the vertical lines. Upon receipt of an input voltage with a gradation level (voltage value) corresponding to an image to be displayed, or upon receipt of a plurality of bit data inputs corresponding to the gradation level, the display driver circuit outputs to a vertical line corresponding thereto an output voltage corresponding to the input voltage.
As a conventional display driver circuit, Japanese Patent Application Publication No. 2001-156559 (patent document 1) is disclosed. Referring to FIG. 3 of patent document 1, the display driver circuit has a P-type MOS differential input part 1 composed of transistors M1, M2, and M3, an N-type MOS differential input part 2 composed of transistors M4, M5, and M6, a current mirror circuit 3 composed of transistors M7, M8, M9, and M10, a current mirror circuit 4 composed of transistors M11, M12, M13, and M14, a push-pull output stage 5 composed of transistors M15 and M16, and phase compensation capacitances C1 and C2. Vdd is a positive side power voltage and Vss is a negative side power voltage.
Operation of the display driver circuit disclosed in patent document 1 (FIG. 3) will be described with reference to FIG. 25. FIG. 25 shows a change in a voltage Vin supplied to the display driver circuit, a voltage Vc at a connection node of the phase compensation capacitances C1 and C2, and an output voltage Vout that the vertical line receives.
Upon shift to a transition mode, the output terminal of the display driver circuit is brought out of connection with the vertical line of the display. Also the voltage value of the input voltage Vin changes. The phase compensation capacitances C1 and C2 charge or discharge electric charge in accordance with the change in the voltage value of the input voltage Vin. As shown in FIG. 25, the voltage Vc at the connection node of the phase compensation capacitances C1 and C2 gradually rises. The rate of the charging/discharging is proportional to the current amounts of currents (tail currents) flowing through the transistors M1 and M6, and inversely proportional to the capacitance values of the phase compensation capacitances C1 and C2. Meanwhile, since the output terminal of the display driver circuit is disconnected from the vertical line, the voltage value of the output voltage Vout supplied to the vertical line remains unchanged.
Next, upon shift to an output mode, the output terminal of the display driver circuit is brought into connection with the vertical line so that the voltage Vc at the connection node of the phase compensation capacitances C1 and C2 is output to the vertical line through an output circuit 5. As shown in FIG. 25, the voltage value of the output voltage Vout gradually rises as the voltage Vc rises.
In addition to patent document 1, Japanese Patent Application Publication Nos. 11-259052 (patent document 2), 2000-295044 (patent document 3), 2003-228353 (patent document 4), and the like are also disclosed.
As a conventional display driver of a dot inversion driving system, Japanese Patent Application Publication No. 2002-14658 (patent document 5) is disclosed. In a display driver 10 of patent document 5 (FIG. 4), positive and negative gradation voltages are supplied to odd-numbered vertical lines and even-numbered vertical lines, respectively. Also a switch 16 is connected between adjacent display driver circuits 14. In this display driver, by turning on and off the switch 16, accumulated electric charge is distributed to each horizontal line, thus attempting to make an efficient use of electric charge.
Operation of (2n−1)th and (2n)th display driver circuits 14 (n being an integer) disclosed in patent document 5 (FIG. 4) will be described with reference to FIG. 26. FIG. 26 shows a change in input voltages Vin(2n−1) and Vin(2n) supplied to the respective display driver circuits, voltages Vc(2n−1) and Vc(2n) across the respective phase compensation capacitances of the display driver circuits, and output voltages Vout(2n−1) and Vout(2n) that the respective vertical lines receive.
First, the display driver circuits 14 respectively output output-voltages Vout(2n−1) and Vout(2n) corresponding to the input voltages Vin(2n−1) and Vin(2n), respectively. Here the phase compensation capacitances of the display driver circuits accumulate an amount of electric charge corresponding to the input voltages Vin(2n−1) and Vin(2n), respectively.
Next, upon shift to the transition mode, the switch 16 is turned on to connect the output terminal of the (2n−1)th display driver circuit 14 to the output terminal of the (2n)th display driver circuit 14. Each switch 15 is turned off to disconnect the output terminal from the vertical line. This causes the accumulated electric charge to be distributed to each vertical line, thus making the voltage values of the output voltages Vout(2n−1) and Vout(2n) median values. Meanwhile, the polarities of the input voltages Vin(2n−1) and Vin(2n) are inversed. As the input voltages Vin(2n−1) and Vin(2n) change, the voltages Vc(2n−1) and Vc(2n) across the respective phase compensation capacitances contained in the display driver circuits 14 gradually rise or fall toward respective target values, as shown in FIG. 26.
Next, upon shift to the output mode, the switch 16 is turned on and the switch 15 is turned off to connect the output terminal of each display driver circuit 14 to each vertical line, thus outputting the voltages Vc(2n−1) and Vc(2n) across the phase compensation capacitances through the respective output circuits. As the voltages Vc(2n−1) and Vc(2n) rise or fall, the voltage values of the output voltages Vout(2n−1) and Vout(2n) gradually rise or fall toward respective target values, as shown in FIG. 26.
In addition to patent document 5, Japanese Patent Publication Nos. 3586998 (patent document 6) and 3063670 (patent document 7), Japanese Patent Application Publication Nos. 2000-39870 (patent document 8), 2000-221932 (patent document 9), 10-133174 (patent document 10), 10-301537 (patent document 11), 2000-39870 (patent document 12), and 2000-221932 (patent document 13), U.S. Pat. Nos. 6,650,312 (patent document 14) and 6,184,855 (patent document 15), and the like are also disclosed.    Patent document 1: Japanese Patent Application Publication No. 2001-156559    Patent document 2: Japanese Patent Application Publication No. 11-259052    Patent document 3: Japanese Patent Application Publication No. 2000-295044    Patent document 4: Japanese Patent Application Publication No. 2003-228353    Patent document 5: Japanese Patent Application Publication No. 2002-14658    Patent document 6: Japanese Patent Publication No. 3586998    Patent document 7: Japanese Patent Publication No. 3063670    Patent document 8: Japanese Patent Application Publication No. 2000-39870    Patent document 9: Japanese Patent Application Publication No. 2000-221932    Patent document 10: Japanese Patent Application Publication No. 10-133174    Patent document 11: Japanese Patent Application Publication No. 10-301537    Patent document 12: Japanese Patent Application Publication No. 2000-39870    Patent document 13: Japanese Patent Application Publication No. 2000-221932    Patent document 14: U.S. Pat. No. 6,650,312    Patent document 15: U.S. Pat. No. 6,184,855